IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 199

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Abnormal Master Transaction Termination
An abnormal transaction termination is one in which the local side did
not explicitly request the termination of a transaction by asserting the
lm_lastn signal. A master transaction can be terminated abnormally for
several reasons. This section describes the behavior of the pci_mt64 and
pci_mt32 functions during the following abnormal termination
conditions:
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Latency Timer Expires
The PCI specification requires that the master device end the transaction
as soon as possible after the latency timer expires and the gntn signal is
deasserted. The pci_mt64 and pci_mt32 functions adhere to this rule,
and when they end the transaction because the latency timer expired,
they assert lm_tsr[4] (tsr_lat_exp) until the beginning of the next
master transaction.
1
Retry
The target issues a retry by asserting stopn and devseln during the first
data phase. When the pci_mt64 and pci_mt32 MegaCore functions
detect a retry condition (refer to
end the cycle and assert lm_tsr[5] until the beginning of the next
transaction. This process informs the local-side device that it has ended
the transaction because the target issued a retry.
1
Latency timer expires
Target retry
Target disconnect without data
Target disconnect with data
Target abort
Master abort
The PCI MegaCore functions allow the option of disabling the
latency timer for embedded applications. Refer to
Master Latency Timer” on page 2–6
The PCI specification requires that the master retry the same
transaction with the same address at a later time. It is the
responsibility of the local-side application to ensure that this
requirement is met.
PCI Compiler Version 10.1
“Retry” on page 3–77
for more information.
Functional Description
for details), they
“Disable
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