IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 212

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Features
Features
PCI Testbench
Files
4–2
PCI Compiler User Guide
The PCI testbench includes the following features:
■
■
■
■
■
■
■
The Altera PCI testbench is included and installed with the PCI Compiler.
Figure 4–2
where <path> is the directory in which the PCI Compiler is installed.
Figure 4–2. PCI Testbench Directory Structure
< path >
Easy to use simulation environment for any standard VHDL or
Verilog HDL simulator
Open source VHDL and Verilog HDL files
Flexible PCI bus functional model to verify your application that
uses any Altera PCI MegaCore function
Simulates all basic PCI transactions including memory read/write
operations, I/O read and write transactions, and configuration read
and write transactions
Simulates all abnormal PCI transaction terminations including target
retry, target disconnect, target abort, and master abort
Simulates PCI bus parking
Includes a simple reference design that performs basic memory and
I/O transactions
pci_compiler
PCI Compiler Version 10.1
shows the directory structure of PCI testbench subdirectory,
megawizard_flow
testbench
< HDL language >
< PCI MegaCore Function >
example
Contains files and scripts allowing you to simulate PCI
transactions
local_bfm
Contains a simple reference design
pci_top
Contains an IP functional simulation model
tb_src
Contains testbench source files
Altera Corporation
January 2011