IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 325

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
0
1
2
3
4
5
6
Table 7–26. Avalon Interrupt Status Register – Address 0x3060 (Part 1 of 2)
Bit
ERR_PCI_WRITE_FAILURE
ERR_PCI_READ_FAILURE
ERR_NONP_DATA_DISCARD
MASTER_ENABLE_FALL
MASTER_ENABLE_RISE
Reserved
INTAN_FALL
Name
Table 7–26
RW1C
RW1C
RW1C
RW1C
RW1C
N/A
RW1C
PCI Compiler Version 10.1
Access
describes the Avalon-MM interrupt status register bits.
Mode
When set to 1 indicates a write to PCI failure either due to
a master or target abort, or because the retry threshold has
been exceeded. This bit can also be cleared by writing '1'
to the same bit in the PCI interrupt status register.
This bit will only be implemented when the bridge is
operating in the PCI Master/Target Peripheral modes or
the PCI Host-Bridge Device mode.
When set to 1 indicates a read from PCI failure either due
to a master or target abort, or because the retry threshold
has been exceeded. This bit can also be cleared by writing
'1' to the same bit in the PCI interrupt status register.
This bit will only be implemented when the bridge is
operating in the PCI Master/Target Peripheral modes or
the PCI Host-Bridge Device mode.
When set to 1 indicates that non-prefetchable data read
from the interconnect is discarded because the PCI read
request was not retried before the parameterized discard
timer expired. This bit can also be cleared by writing '1' to
the same bit in the PCI interrupt status register.
This bit will only be implemented when the
non-prefetchable Avalon-MM master port is implemented.
This bit is set to 1 when the PCI command register master
enable bit (command register bit 2) falls from 1 to 0. This
bit is set to 0 when '1' is written to it and master enable does
not transition in the same cycle as the write.
This bit is only implemented when the bridge is operating
in the PCI Master/Target Peripheral modes or the PCI
Host-Bridge Device mode.
This bit is set to 1 when the PCI command register master
enable bit (command register bit 2) rises from 0 to 1. This
bit is set to 0 when '1' is written to it and master enable does
not transition in the same cycle as the write.
This bit is only implemented when the bridge is operating
in the PCI Master/Target Peripheral modes or the PCI
Host-Bridge Device mode.
This bit is set to 1 when the PCI
from 1 to 0. This bit is set to 0 when '1' is written to it and
intan
This bit is only implemented when the bridge is operating
in the PCI Host-Bridge Device mode.
does not transition in the same cycle as the write.
Description
intan
Functional Description
signal changes
7–57