IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 289

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
PCI-to-Avalon non-prefetchable command register is
full. Current command, address and byte enables do
not match this register.
PCI-to-Avalon non-prefetchable command register is
full. Current command, address and byte enables
match this register. However, response data from the
interconnect is not available.
PCI-to-Avalon non-prefetchable command register is
full. Current command, address and byte enables
match this register. Response data from the
interconnect is valid.
PCI-to-Avalon non-prefetchable command register is
available.
PCI-to-Avalon non-prefetchable command register is
available. Avalon-to-PCI write operation is already
pending.
Target abort
Table 7–5. Non-Prefetchable Read Operation
Request/Termination Condition
Table 7–5
non-prefetchable PCI target read operations.
Prefetchable Operations
If you select either of the burst performance profiles (Burst Transfers with
Single Pending Read or Burst Transfers with Multiple Pending Reads),
requests that hit prefetchable BARs are handled by the prefetchable data
path. At the same time, request that hit non-prefetchable BARs are
handled by the non-prefetchable data path as previously described.
The prefetchable data path supports both single-cycle and burst
operations and allows multiple writes to be internally pipelined.
Additionally, if you select Burst Transfers with Multiple Pending Reads
target performance profile, the prefetchable data path will support up to
four pending read operations. The Burst Transfers with Single Pending
Read target performance profile allows only one pending read at a time.
shows all of the termination conditions that are possible for
PCI Compiler Version 10.1
The target controller retries the operation on the PCI
bus. Nothing is remembered about the retried PCI read
operation. When the PCI read operation is
subsequently re-issued, it is treated as a new
operation.
The target controller retries the operation on the PCI
bus.
The data is returned to the PCI bus and a disconnect is
signaled. The PCI-to-Avalon non-prefetchable
command register is made available.
Address, command, and byte enables are captured in
the PCI-to-Avalon non-prefetchable command register.
The read request is forwarded to the interconnect. A
retry is signaled on the PCI bus.
Address, command, and byte enables are captured in
the PCI-to-Avalon non-prefetchable command register.
The read request is forwarded to the interconnect. A
retry is signaled on the PCI bus. The returned read data
is not made available until the previously pending
Avalon-to-PCI write operations are complete.
Not applicable. The target controller will not terminate
a PCI read operation with a target abort.
Resulting Action
Functional Description
7–21