IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 317

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
0x0040
0x0050
0x0800-0x081F
0x0900-0x091F
0x1000-0x1FFF
0x2C00
0x2C04
0x2C08
0x3060
0x306C
0x3070
0x3A00–0x3A1F
0x3B00–0x3B1F
Table 7–17. PCI-Avalon Bridge Register Map
Address Range
Table 7–17
The following sections describe the control and status registers in detail.
In describing the register’s bits, the following nomenclature is used:
■
■
■
PCI Interrupt Status Register
The PCI interrupt status register contains the status of various events in
the PCI-Avalon bridge logic and allows PCI interrupts to be signaled if
the indicated status bit is set while the corresponding bit in the PCI
interrupt enable register is also set. This register is intended to be accessed
only by other PCI masters; however, there is nothing in the hardware that
prevents other Avalon-MM masters from accessing it.
PCI interrupt status register
PCI interrupt enable register
PCI-to-Avalon mailbox registers – read/write
Avalon-to-PCI mailbox registers – read only
Avalon-to-PCI address translation table
General configuration parameters – read only
Performance parameters – read only
Avalon-to-PCI address translation parameters – read only
Avalon interrupt status register
Current PCI status register – read only
Avalon interrupt enable register
Avalon-to-PCI mailbox registers – read/write
PCI-to-Avalon mailbox registers – read only
RO: Read only bit. The value of RO bits cannot be modified, but can
be read.
RW: Read and write. The value of RW bits can be read and written.
RW1C: Read and write "1" to clear. The RW1C bits can be read, but
can only be cleared by writing a 1 to the bit location.
PCI Compiler Version 10.1
shows the complete map of registers.
Register
Functional Description
7–49