IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 121

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
ack64n signals in the pci_mt64 and pci_t64 functions are asserted
three clock cycles after a valid address is presented on the PCI bus). In all
operations except configuration read/write, one of the lt_tsr[5..0]
signals is driven high, indicating the BAR range address of the current
transaction.
Configuration transactions are always single-cycle 32-bit transactions.
The PCI MegaCore function has complete control over configuration
transactions and informs the local-side device of the progress and
command of the transaction. The PCI MegaCore function asserts all
control signals, provides data in the case of a read, and receives data in
the case of a write without interaction from the local-side device.
Memory transactions can be single-cycle or burst. In target mode, the PCI
MegaCore function supports an unlimited length of zero-wait state
memory burst read or write transactions. In a read transaction, data is
transferred from the local side to the PCI master. In a write transaction,
data is transferred from the PCI master to the local-side device. A
memory transaction can be terminated by either the PCI master or the
local-side device. The local-side device can terminate the memory
transaction using one of three types of terminations: retry, disconnect, or
target abort.
how to initiate the different types of termination.
1
I/O transactions are always single-cycle 32-bit transactions. Therefore,
the PCI MegaCore function handles them like single-cycle memory
commands. Any of the six BARs in the PCI MegaCore functions can be
configured to reserve I/O space. Refer to
page 3–37
an I/O BAR. Like memory transactions, I/O transactions can be
terminated normally by the PCI master, or the local-side device can
instruct the PCI MegaCore function to terminate the transactions with a
retry or target abort. Because all I/O transactions are single-cycle,
terminating a transaction with a disconnect does not apply.
The PCI MegaCore function treats the memory read line and
memory read multiple commands as memory read. Similarly,
the function treats the memory write and invalidate command
as a memory write. The local-side application must implement
any special requirements for these commands.
PCI Compiler Version 10.1
for more information on how to configure a specific BAR to be
“Target Transaction Terminations” on page 3–77
“Base Address Registers” on
Functional Description
describes
3–47