IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 331

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

General
Description
Altera Corporation
January 2011
The Altera PCI testbench facilitates the design and verification of systems
that implement the Altera PCI-Avalon bridge. The testbench is provided
in both VHDL and Verilog HDL. When you build your system with the
PCI-Avalon bridge, SOPC Builder automatically integrates the PCI
testbench with your system testbench files.
SOPC Builder creates the pci_sim directory in your project directory and
copies all the PCI testbench files from <path>/pci_compiler/
sopc_flow/testbench/<language>/<core> into
<project directory>/pci_sim.
1
Figure 8–1
blocks are provided with the PCI testbench.
The testbench files must be edited to add the PCI transactions
that will be performed on the system. If you regenerate your
system, SOPC Builder will not overwrite the testbench files in
the pci_sim directory. If you want the default testbench files,
first delete the pci_sim directory and then regenerate your
system.
PCI Compiler Version 10.1
shows the block diagram of the PCI testbench. The shaded
8. Testbench
8–1