IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 255

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
PCI Master Performance
This field lists the two available PCI master performance profile options.
The wizard uses your selections to determine read and write operation
throughput generated by Avalon-MM master devices to PCI target
devices.
This section defines the following PCI master performance profile
options:
■
■
Burst Transfers with Single Pending Read
This option allows burst and single-cycle accesses from Avalon-MM
master devices, which includes memory, I/O, and configuration
transactions.
The PCI-Avalon bridge contains either a dynamic or fixed Avalon-to-PCI
address translation table. Depending on the address translation entry, the
corresponding PCI address and command is generated by the
PCI-Avalon bridge.
In this mode, only one pending read is serviced at a time. All subsequent
reads are stored in a temporary queue holding up to eight transactions
until the current pending read transaction is finished. If read transactions
can be stored in the temporary read queue, write transactions are allowed
to pass the read transactions.
Select the Burst Transfers with Single Pending Read performance
profile either for:
■
■
Burst Transfers with Multiple Pending Reads
This option is similar to the Burst Transfers with Single Pending Read
option except that it allows up to four pending reads. In other words,
instead of issuing one read at a time, up to four simultaneous reads can
be issued on the PCI bus. This allows PCI target devices to return read
data while also reducing the read completion times.
Burst Transfers with Single Pending Read
Burst Transfers with Multiple Pending Reads
General purpose systems
Data-intensive systems that utilize write operations to move data
and use minimum read operations
PCI Compiler Version 10.1
Parameter Settings
6–5