IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 275

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 7–2. PCI-Avalon Bridge Managing the PCI Target-Only Peripheral Mode, Single-Cycle Transfers Only
Altera Corporation
January 2011
Processor
Master/
Device
Target
Arbiter
Host
PCI
Bus
PCI
PCI
Bus
MegaCore
Function
PCI
Figure 7–3
the connectivity of the PCI Target-Only Peripheral mode with either the
Burst Transfers with Single-Pending Read profile or the Burst Transfers
With Multiple Pending Reads performance profile. The configuration
uses two of the four Avalon-MM ports and has a Host processor and bus
arbiter on the PCI side.
1
With Single-Cycle Transfers Only
Controller
Target-Only Peripheral Mode
Target
PCI
Because both the Prefetchable and Non-Prefetchable
Avalon-MM master ports are instantiated, the Avalon bridge
must have at least two memory BARs; one prefetchable memory
BAR and one non-prefetchable memory BAR.
PCI-Avalon Bridge
PCI Compiler Version 10.1
shows the block diagram of the PCI-Avalon bridge managing
Prefetchable
Bridge Logic
Non-
PCI
Prefetchable
Avalon
Master
Non-
Interconnect
System
Functional Description
Fabric
Peripheral
Avalon
Slave
7–7