IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 134

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–12. 32-Bit PCI and 64-Bit Local-Side Burst Memory Read Target Transaction
Note to
(1)
3–60
PCI Compiler User Guide
l_adro[31..0]
l_cmdo[3..0]
l_adi[63..32]
l_hdat_ackn
l_beno[7..4]
l_beno[3..0]
l_ldat_ackn
lt_tsr[11..0]
l_adi[31..0]
cben[3..0]
lt_framen
ad[31..0]
devseln
The value on ad[31..0] is not a QWORD address boundary (ad[2..0] == B”100”).
lt_dxfrn
ack64n
lt_ackn
framen
req64n
lt_rdyn
stopn
trdyn
irdyn
par
clk
Figure
1
3–12:
2
Adr (1)
000
6
3
Adr-PAR
Adr PAR
4
Z
Z
PCI Compiler Version 10.1
5
BE0_H
6
BE0_H
301
D0_H
D0_L
7
BE0_H
D1_H
D1_L
8
D0_H
Adr
6
9
D0-H-PAR
BE1_L
BE1_L
BE2_H
D1_L
D2_H
D2_L
10
701
D1-L-PAR
BE1_H
D1_H
D1_H
BE2_H
Altera Corporation
11
D1-H-PAR
January 2011
12
000
13