IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 190

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–116
PCI Compiler User Guide
Figure 3–41
bus target inserting a wait state. This figure applies to both the pci_mt64
and pci_mt32 MegaCore functions, excluding the 64-bit extension
signals as noted for pci_mt32. The PCI target inserts a wait state by
deasserting trdyn in clock cycle 9. Consequently, on the following clock
cycle (clock cycle 10), the pci_mt64 and pci_mt32 functions deassert
the lm_ackn and lm_dxfrn signals on the local side. Data transfer is
suspended on the PCI side in clock cycle 9 and on the local side in clock
cycle 10. Also, because lm_lastn is asserted and lm_rdyn is deasserted
in clock cycle 11, the lm_ackn and lm_dxfrn signals remain deasserted
after clock cycle 12.
PCI Compiler Version 10.1
shows the same transaction as in
Figure 3–38
Altera Corporation
but with the PCI
January 2011