IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 62

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Advanced PCI MegaCore Function Features
2–4
PCI Compiler User Guide
Optional Interrupt Capabilities
The PCI MegaCore functions support optional PCI interrupt capabilities.
For example, if an application uses the interrupt pin, the interrupt pin
register indicates that the interrupt signal (intan) is used by storing a
value of 0x01 in the interrupt pin register. Turning off Use Interrupt Pin
on the Advanced PCI MegaCore Function Features page results in the
interrupt pin register being set to 0x00.
The PCI MegaCore functions also include an option to respond to the
interrupt acknowledge command. If Support Interrupt Acknowledge
Command is turned off, the PCI MegaCore function ignores the interrupt
acknowledge command. When Support Interrupt Acknowledge
Command is turned on, the PCI MegaCore function responds to the
interrupt acknowledge command by treating it as a regular target
memory read. The local side must implement the logic necessary to
respond to the interrupt acknowledge command.
For more information on the capabilities list pointer, CIS cardbus pointer,
and interrupt pin registers, refer to
page
Master Features
The pci_mt64 and pci_mt32 MegaCore functions also provide the
following options available in the Parameterize - PCI Compiler wizard:
■
■
■
■
■
Enable these features on the Advanced PCI MegaCore Function Features
page as described in the following sections.
Allow Variable Byte Enables During Burst Transactions
Use in Host Bridge Application
Allow Internal Arbitration Logic
Disable Master Latency Timer
Assume ack64n Response
3–28.
PCI Compiler Version 10.1
“Configuration Registers” on
Altera Corporation
January 2011