IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 293

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
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To optimize overall performance, PCI memory read line and memory
read multiple requests (that use linear burst order) always have their
burst lengths rounded to a burst boundary. This is done so that
subsequent reads will be naturally aligned to burst boundaries.
When a previously remembered PCI read request is claimed again, it is
retried until there is at least one data phase worth of data in the response
buffer. When there is at least one data phase worth of data in the response
buffer, the burst data transfer will begin.
Every attempt is made to keep the read burst transfer going for as long as
possible. If additional data has been requested from Avalon-MM, but is
not yet available in the response buffer, wait states are inserted on the PCI
bus up to the PCI specified maximum target subsequent latency of eight
cycles. As soon as the response data is available, it is transferred to the
PCI bus. If the data is not available within the eight clock cycles, a target
disconnect is issued.
Any time the PCI read operation ends (via either the master or the target
device), any prefetched data remaining in the response buffer—or still
expected from the interconnect—is discarded. This is done to be consistent
with the PCI-SIG specifications.
For memory read requests that hit a prefetchable BAR, all bytes are
enabled in the Avalon-MM requests regardless of the actual byte enables
signaled by the PCI master.
Associated with each pending read response buffer is a timer that
determines if and when to discard the data read from the interconnect
and free the pending read response buffer. When the initial data for a
prefetchable read request is returned from the interconnect, the timer is
initialized to 2047 and the timer begins counting down. If the timer
reaches 0 before the matching PCI read request is repeated, the data is
discarded and the pending read request buffer is freed. Discarding
prefetchable read data is not considered an error and no status bit is set
to indicate that this has happened.
The PCI memory read command initiates burst transaction to the
Avalon bus with the burst value based on the maximum target read
burst size (refer to
For example, the read transaction will return maximum number of
32 DWORDs when the maximum target read burst value is 32.
PCI Compiler Version 10.1
“Maximum Target Read Burst Size” on page
Functional Description
6–4).
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