IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 227

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
BAR2
BAR2
BAR2
Address Space Range Reserved
Table 4–9. BAR2 Register Mapping
00h-03h
04h-07h
08h-0Bh
Local Target
The local target consists of a simple state machine that performs 32- or
64-bit memory read/write transactions with the LPM memory and 32-bit
single-cycle I/O read/write transactions with an I/O register defined in
the local target. The local target uses prefetch logic for burst read
transactions and ignores byte enables for all memory and I/O
transactions.
Depending on the value of the target termination register, the local target
performs the terminations in
DMA Engine
The DMA engine has two 32-bit registers, which are mapped to BAR2 in
the PCI MegaCore function.
registers on BAR2.
To initiate a master transaction from a PCI MegaCore function, use the
master transactor to perform memory writes to these locations with the
appropriate values.
The dma_sa register defines the system address used for the PCI
transaction. This address is driven during the address phase of the PCI
transaction. Normally, the address written here is the base address
register value of the PCI testbench target transactor.
xxxxxxx0
xxxxxxx1
xxxxxxx2
Table 4–10. Target Terminations
targ_termination_reg Setting
targ_termination_reg Target termination register.
dma_sa[31:0]
dma_bc_la[31:0]
PCI Compiler Version 10.1
Mnemonic
Table 4–9
shows the BAR2 register mapping.
DMA system address register
DMA byte count and local address register
Table 4–9
Table
4–10.
Normal Termination
Target Retry
Disconnect
describes the mapping of DMA
Register Name
Target Termination
PCI Compiler User Guide
Testbench
4–17