IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 112

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
3–38
PCI Compiler User Guide
0
2..1
3
31..4
Table 3–23. Memory BAR Format
Data
Bit
mem_ind
mem_type
pre_fetch
bar
Mnemonic
Read
Read
Read
Read/write
Read/Write
Table 3–23
In addition to the type of space reserved by the BAR, the wizard allows
you to define the size of address space reserved for each individual BAR
and sets the BARn parameter value accordingly. The value for parameter
BARn defines the number of read/write bits instantiated in the
corresponding BAR (Refer to Section 6.2.5 of the PCI Local Bus
Specification, Revision 3.0). The number of read/write bits instantiated in a
BAR is indicated by the number of 1s in the corresponding BARn value
starting from bit 31. The BARn parameter should contain 1s from bit 31
down to the required bit without any 0s in between (e.g., 0xFF000000 is
legal, but 0xFF700000 is not). The wizard does not offer options that set
the BARn parameters to illegal values.
For high-end systems that require more than 4 GBytes of memory space,
the pci_mt64 and pci_t64 functions support 64-bit addressing. These
functions offer the option to use either BARs 1 and 0 or BARs 2 and 1 to
implement a 64-bit BAR.
When implementing a 64-bit BAR, the least significant BAR contains the
lower 32-bit BAR and the most significant BAR contains the upper 32-bit
BAR. When implementing a 64-bit BAR, the wizard allows the option of
which BARs to use and sets the BARn parameters accordingly. On the
least significant BAR, bits [31..4] are read/write registers that are used
to indicate the size of the memory, along with the most significant BAR.
For the most significant BAR, the wizard allows you to choose the
maximum number of read/write registers to implement per the
application.
Memory indicator. The
memory address space. This bit must be set to 0 in the BARn parameter.
Memory type. The
be implemented in the function’s memory address space. Only the
following two possible values are valid for the PCI MegaCore functions:
locate memory space in the 32-bit address space and locate memory
space in the 64-bit address space.
Memory prefetchable. The
of memory are prefetchable by the host bridge.
Base address registers.
PCI Compiler Version 10.1
shows the format of memory BARs.
mem_type
mem_ind
pre_fetch
Definition
bits indicate the type of memory that can
bit indicates that the register maps into
bit indicates whether the blocks
Altera Corporation
January 2011