IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 118

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Target Mode
Operation
3–44
PCI Compiler User Guide
clk
rstn
gntn
reqn
ad[63..0]
cben[7..0]
par
par64
idsel
framen
req64n
irdyn
devseln
ack64n
Table 3–34. PCI MegaCore Function Signals (Part 1 of 3)
Signal Name
pci_mt64
Maximum Latency Register
The maximum latency register is an 8-bit read-only register that defines
the frequency in which the function would like to gain access to the PCI
bus. Refer to
This section describes all supported target transactions for the PCI
MegaCore functions. Although this section includes waveform diagrams
showing typical PCI cycles in target mode for the pci_mt64 MegaCore
function, these waveforms are also applicable for the pci_mt32,
pci_t64, and pci_t32 MegaCore functions. The pci_mt64 and
pci_t64 MegaCore functions support both 32-bit and 64-bit
transactions.
each PCI function.
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Table 3–33. Maximum Latency Register Format
Data Bit
7..0
PCI Compiler Version 10.1
Table
Table 3–34
PCI Signals
3–33. You can set this register through the wizard.
pci_t64
Mnemonic
max_lat
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lists the PCI and local side signals that apply for
ad[31..0]
cben[3..0]
Read/Write
Read
pci_mt32
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Maximum latency register
ad[31..0]
cben[3..0]
Altera Corporation
Definition
January 2011
pci_t32
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