IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 93

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
l_cmdo[3..0]
l_ldat_ackn
l_hdat_ackn
Table 3–6. PCI Local Address, Data, Command & Byte Enable Signals (Part 3 of 3)
Name
Output
Output
Output
Type
–
Low
Low
Polarity
PCI Compiler Version 10.1
Local command output. The
MegaCore functions during target transactions. It has the bus
command and the same timing as the
command is encoded as presented on the PCI bus.
Local low data acknowledge. The
during target write and master read transactions. When asserted,
l_ldat_ackn
transferred on the
is asserted, the address of the transaction is on a
(
used to qualify valid data.
During target read transactions,
the first
transaction is a
asserted.
This signal is not implemented in the
functions.
Local high data acknowledge. The
during target write and master read transactions. When asserted,
l_hdat_ackn
transferred on the
l_hdat_ackn
QWORD
or
During target read transactions,
the first
transaction is not a
and
This signal is not implemented in the
functions.
ad[2..0]
lt_ackn
l_hdat_ackn
boundary (
DWORD
DWORD
=
must be used to qualify valid data.
B"000
QWORD
transferred to the PCI side. If the address of the
transferred to the PCI side. If the address of the
indicates that the least significant
indicates that the most significant
is asserted, the address of the transaction is not a
l_dato[31..0]
l_dato[31..0]
ad[2..0] = B"100
QWORD
is asserted.
"
). The signals
boundary, the
boundary,
l_cmdo[3..0]
Description
l_ldat_ackn
l_hdat_ackn
l_ldat_ackn
l_hdat_ackn
lm_ackn
pci_mt32
pci_mt32
bus, i.e., when
bus. In other words, when
l_ldat_ackn
l_ldat_ackn
l_adro[31..0]
"
). The signals
Functional Description
bus is driven by the PCI
or
is used to indicate
is used to indicate
and
and
QWORD
lt_ackn
DWORD
output is used
DWORD
output is used
l_ldat_ackn
pci_t32
pci_t32
signal is
is deasserted
lm_ackn
bus. The
boundary
is being
is being
must be
3–19