IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 314

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interrupts
Interrupts
7–46
PCI Compiler User Guide
When no ArbReq_n_i lines are asserted, ArbGnt_n_o[0] will be
asserted, parking the bus on the internal PCI-Avalon bridge master.
This section discusses the generation and reception of PCI and
Avalon-MM interrupts.
Generation of PCI Interrupts
There are several events that can cause a PCI interrupt. However, for each
event there is a specific bit that enables the interrupt. The following
events can cause a PCI interrupt:
■
■
■
In any SOPC Builder constructed PCI-Avalon system, either the
prefetchable or the non-prefetchable master port has an Avalon-MM
interrupt (IRQ) input. The non-prefetchable master port always has the
IRQ interrupt input. However, if the non-prefetchable master is not
implemented in a system, the prefetchable port will have the IRQ
interrupt input.
The Avalon-MM IRQ input causes a bit to be set in the PCI interrupt
status register. When you need to assert a PCI interrupt, this bit can be
enabled.
PCI interrupts can also be generated by writing to the Avalon-to-PCI
mailbox registers and having the appropriate enable bit set.
PCI interrupts can also be signaled under a variety of error conditions.
Refer to the PCI interrupt status register
the PCI interrupt enable register
list of possible interrupt conditions.
Reception of PCI Interrupts
If it is enabled, the PCI-Avalon bridge can signal an interrupt on the
interconnect—in response to the assertion or deassertion of the PCI
interrupt signal. The PCI-Avalon bridge provides register bits that can
signal either a falling- or a rising-edge of the PCI interrupt signal inta.
You can specify to signal an Avalon-MM interrupt in response to either of
the two events or both events.
Avalon asserts the IRQ signal
Avalon writes to one of the mailbox registers
An error condition is detected
PCI Compiler Version 10.1
(Table 7–19 on page
(Table 7–18 on page
7–52) for a complete
Altera Corporation
January 2011
7–50) and