IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 217

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Target abort
Target retry
Target disconnect
Table 4–5. PCI Testbench Target Termination Support
Features
Master Transactor
Table 4–5
transactor and the local master respond to the target terminations by
terminating the transaction gracefully and releasing the PCI bus.
Master Transactor (mstr_tranx)
The master transactor simulates the master behavior on the PCI bus. It
serves as an initiator of PCI transactions for Altera PCI testbench. The
master transactor has three main sections:
■
■
■
PROCEDURES and TASKS Sections
The PROCEDURES (VHDL) and TASKS (Verilog HDL) sections define
the events that are executed for the user commands supported by the
master transactor. The events written in the PROCEDURES and TASKS
sections follow the phases of a standard PCI transaction as defined by the
PCI Local Bus Specification, Revision 3.0, including:
■
■
■
■
The master transactor terminates the PCI transactions in the following
cases:
■
■
■
v
v
v
PROCEDURES (VHDL) or TASKS (Verilog HDL)
INITIALIZATION
USER COMMANDS
Address phase
Turn-around phase (read transactions)
Data phases
Turn-around phase
The PCI transaction has successfully transferred all the intended data
The PCI target terminates the transaction prematurely with a target
retry, disconnect, or abort as defined in the PCI Local Bus Specification,
Revision 3.0
A target does not claim the transaction resulting in a master abort
shows the testbench's target termination support. The master
PCI Compiler Version 10.1
Target Transactor
v
v
Local Master
v
v
v
PCI Compiler User Guide
Local Target
v
v
Testbench
4–7