IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 271

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Figure 7–1. Generic PCI-Avalon Bridge Block Diagram
Avalon-MM Ports
The Avalon bridge is comprised of up to four (depending on device
operating mode) predefined ports to communicate with the interconnect.
This section discusses the four Avalon-MM ports:
■
■
■
■
Prefetchable Avalon-MM Master
The prefetchable Avalon-MM master port provides a high bandwidth
PCI memory request access to Avalon-MM slave peripherals. This master
port is capable of generating Avalon-MM burst requests for PCI requests
that hit a prefetchable base address register (BAR). You should only
connect prefetchable Avalon-MM slaves to this port, typically RAM or
ROM memory devices.
PCI
Bus
Prefetchable Avalon-MM master
Non-Prefetchable Avalon-MM master
PCI bus access slave
Control register access Avalon-MM slave
MegaCore
PCI Bus
Function
Arbiter
PCI Compiler Version 10.1
PCI
Controller
Controller
Master
Target
PCI
PCI
PCI-Avalon Bridge
Prefetchable
Prefetchable
Bridge Logic
Registers
Control
Master
Status
Bridge
Bridge
Logic
Non-
Logic
PCI
PCI
Access Avalon
Prefetchable
Prefetchable
Register
Control
PCI Bus
Avalon
Master
Access
Avalon
Master
Functional Description
Slave
Non-
Slave
Interconnect
System
Fabric
7–3