IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 83

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Master Device Signals & Signal Assertion
Figure 3–6
connect to the PCI bus. The signals are grouped by functionality, and
signal directions are illustrated from the perspective of a PCI MegaCore
function operating as a master on the PCI bus.
master signals. The 64-bit extension signals, including req64n, ack64n,
par64, ad[63..32], and cben[7..4], are not implemented in the
pci_mt32 function.
Figure 3–6. Master Device Signals
A 32-bit master sequence begins when the local side asserts lm_reqn32n
to request mastership of the PCI bus. The PCI MegaCore function then
asserts reqn to request ownership of the PCI bus. After receiving gntn
from the PCI bus arbiter and after the bus idle state is detected, the
function initiates the address phase by asserting framen, driving the PCI
address on ad[31..0], and driving the bus command on cben[3..0]
for one clock cycle.
1
Arbitration
Command
Address,
Interface
System
Control
Signals
Signals
Signals
Signals
Data &
For 64-bit addressing, the master generates a dual-address cycle
(DAC). On the first address phase, the pci_mt64 function
drives the lower 32-bit PCI address on ad[31..0], the upper
32-bit PCI address on ad[63..32], the DAC command on
cben[3..0], and the transaction command on cben[7..4].
On the second address phase, the pci_mt64 function drives the
upper 32-bit PCI address on ad[31..0] and the transaction
command on cben[3..0].
PCI Compiler Version 10.1
illustrates the PCI-compliant master device signals that
cben[7..0]
ad[63..0]
devseln
ack64n
req64n
framen
par64
stopn
trdyn
irdyn
idsel
reqn
gntn
rstn
par
clk
Master Device
Figure 3–6
Functional Description
intan
perrn
shows all
Error
Reporting
Signal
Interrupt
Request
Signal
3–9