IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 333

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Testbench
Files
Altera Corporation
January 2011
The Altera PCI testbench is included and installed with the PCI Compiler.
Figure 8–2
subdirectory in the project directory.
1
Figure 8–2. PCI Testbench Directory Structure
Table 8–1
pci_sim/<HDL language>/<core> directory. For more information on
these files, refer to
mstr_tranx
mstr_pkg
trgt_tranx
trgt_tranx_mem_init.dat This file is the memory initialization file for the target
monitor
arbiter
pull_up
Table 8–1. Files Contained in the pci_sim/<HDL language>/<core>
Directory (Part 1 of 2)
You will probably modify the PCI testbench directory to
simulate your design, so SOPC Builder will not overwrite the
<core> directory when you regenerate the SOPC Builder system.
To revert back to the default PCI testbench settings at
regeneration time, just delete the pci_sim directory.
File(1)
gives a description of the PCI testbench files provided in the
PCI Compiler Version 10.1
shows the directory structure of the PCI testbench
“Testbench Specifications” on page
< project directory >
pci_sim
The master transactor defines the procedures
(VHDL) or tasks (Verilog HDL) that initiate PCI
transactions in the testbench.
The master package consists of descriptions of
procedures (VHDL) or tasks (Verilog HDL) for master
transactor (mstr_tranx) commands.
The target transactor simulates the target behavior in
the testbench and responds to PCI transactions.
transactor.
This module monitors the PCI transactions on the
bus and reports the results.
This module contains the PCI bus arbiter.
This module provides weak pull-up on the tri-stated
signals.
< HDL language >
< core >
Contains PCI testbench files
Description
PCI Compiler User Guide
8–4.
Testbench
8–3