IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 332

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Features
Figure 8–1. Altera PCI Testbench Block Diagram
Features
8–2
PCI Compiler User Guide
Testbench Modules
Transactor
Transactor
Pull Ups
Master
Monitor
Target
Arbiter
Bus
To use the PCI testbench, be sure you have a basic understanding of PCI
bus architecture and operations.This document describes the features
and applications of the PCI testbench to help you successfully design and
verify your design.
The PCI testbench includes the following features:
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■
■
■
■
■
Easy to use simulation environment for any standard VHDL or
Verilog HDL simulator
Open source VHDL and Verilog HDL files
Flexible PCI bus functional model to verify your application that
uses any Altera PCI MegaCore function
Simulates all basic PCI transactions including memory read/write
operations, I/O read/write transactions, and configuration
read/write transactions
Simulates all abnormal PCI transaction terminations including target
retry, target disconnect, target abort, and master abort
Simulates PCI bus parking
PCI Bus
PCI Compiler Version 10.1
Altera Device
Using SOPC Builder
System Generated
Compiler
Altera
PCI
Altera PCI Testbench
Interconnect
System
Fabric
Memory
On-chip
Engine
DMA
Altera Corporation
January 2011