IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 343

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
To model different target terminations, use the following three input
signals:
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■
■
The target transactor has two main sections:
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■
FILE IO section
Upon reset, this section initializes the target transactor memory array
with the contents of the trgt_tranx_mem_init.dat file, which must be in
the project's working directory. Each line in the trgt_tranx_mem_init.dat
file corresponds to a memory location, the first line corresponding to
offset "000". The number of lines defined by the address_lines
parameter in the target transactor source code should be equal to number
of lines in the trgt_tranx_mem_init.dat file. If the number of lines in
trgt_tranx_mem_init.dat file is less than the number of lines defined by
the address_lines parameter, the remaining lines in the memory array
are initialized to 0.
PROCEDURES and TASKS sections
The PROCEDURES section (VHDL) and the corresponding TASKS
section (Verilog HDL) define the events to be executed for the decoded
PCI transaction. These sections are fully documented in the source code.
You can modify the procedures or tasks to introduce different variations
in the PCI transactions as required by your application. You can also
create new procedures or tasks that are not currently implemented in the
target transactor by using the existing procedures or tasks as an example.
Bus Monitor (monitor)
The bus monitor displays PCI transactions and information messages to
the simulator's console window and in the log.txt file when an event
occurs on the PCI bus. The bus monitor also sends the PCI transaction
status to the master transactor. The bus monitor reports the following
messages:
trgt_tranx_retry—The target transactor retries the memory
transaction if trgt_tranx_retry is set to one
trgt_tranx_discA—The target transactor terminates the memory
transaction with data if trgt_tranx_discA is set to one
trgt_tranx_discB—The target transactor terminates the memory
transaction with a disconnect without data if trgt_tranx_discB
is set to one
FILE IO
PROCEDURES (VHDL) and TASKS (Verilog HDL)
PCI Compiler Version 10.1
PCI Compiler User Guide
Testbench
8–13