IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 117

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Interrupt Line Register
The interrupt line register is an 8-bit register that defines to which system
interrupt request line (on the system interrupt controller) the intan
output is routed. The interrupt line register is written by the system
software upon power-up; the default value is 0x00.
format of the Interrupt Line Register.
1
Interrupt Pin Register
The interrupt pin register is an 8-bit read-only register that defines the
PCI function PCI bus interrupt request line to be intan. The default
value of the interrupt pin register is 0x01. Refer to
Minimum Grant Register
The minimum grant register is an 8-bit read-only register that defines the
length of time the function would like to retain mastership of the PCI bus.
The value set in this register indicates the required burst period length in
250-ns increments. You can set this register through the wizard. Refer to
Table
Table 3–30. Interrupt Line Register Format
Table 3–31. Interrupt Pin Register Format
Table 3–32. Minimum Grant Register Format
Data Bit
Data Bit
Data Bit
3–32.
7..0
7..0
7..0
The interrupt pin can be enabled or disabled in the wizard. The
interrupt pin register will be set to 0x00 if the interrupt option is
disabled in the Parameterize - PCI Compiler wizard.
PCI Compiler Version 10.1
Mnemonic
Mnemonic
int_pin
int_ln
Mnemonic
min_gnt
Read/Write
Read/write
Read/Write
Read/Write
Read
Read
Interrupt line register
Table
Functional Description
Minimum grant register
Table 3–30
Interrupt pin register
Definition
Definition
3–31.
Definition
shows the
3–43