IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 342

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench Specifications
8–12
PCI Compiler User Guide
Target Transactor (trgt_tranx)
The testbench target transactor simulates the behavior of a target agent on
the PCI bus. The master transactions initiated by the Altera PCI
MegaCore function under test should be addressed to the target
transactor. The target transactor operates in 32- or 64-bit mode. The target
transactor implements two base address registers BAR0 and BAR1. Refer
to
The base address registers define the target transactor address space.
Refer to
The memory range reserved by BAR0 is defined by the address_lines
and mem_hit_range settings in the target transactor source code.
The target transactor has a 32-bit register that stores data for I/O
transactions. This register is mapped to BAR1 of the configuration
address space. Because this is the only register that is mapped to BAR1,
any address that is within the BAR1 range results in an io_hit action.
Refer to the target transactor source code to see how the address is
decoded for io_hit.
1
The target transactor idsel signal should be connected to one of the PCI
address bits in the top-level file of the PCI testbench for configuration
transactions to occur on BAR0 and BAR1.
Table 8–5. Target Transactor Configuration Address Space
Table 8–6. Target Transactor Address Space Allocation
Table
Configuration
Register
BAR0
BAR1
Configuration Register
8–5.
Table
The target transactor ignores byte enables for all memory, I/O,
and configuration transactions.
PCI Compiler Version 10.1
8–6.
BAR0
BAR1
Memory Mapped
Address Space
I/O Mapped
Type
Block Size
Configuration Address Offset
16 Bytes
1 KByte
x10
x14
Altera Corporation
Address Offset
January 2011
000-3FF
0-F