IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 44

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simulate the Design
1–10
PCI Compiler User Guide
f
This section of the walkthrough uses the following:
■
■
■
■
For this walkthrough, follow these steps:
1.
2.
3.
4.
5.
For more information on simulation using NativeLink, refer to
Simulating Altera IP in Third-Party Simulation Tools
the Quartus II Handbook.
The IP toolbench-generated PCI testbench in the
c:\altera\projects\pci_project_nativelink\verilog\pci_mt64
directory
The IP functional simulation model generated as specified in
2: Set Up Simulation” on page 1–7
The ModelSim
The generated NativeLink script in the project directory,
c:\altera\projects
On the EDA Tool Option page in the Quartus II software (Tools >
Options > EDA Tools Option), set the location of the ModelSim
executable .
1
At the Quartus II Tcl Console, run the following command:
source pci_top_nativelink.tcl
On the Simulation page (Assignments > EDA Tools Settings >
Simulation), do the following:
●
●
Perform analysis and synthesis to create the required netlist.
Run the simulation.
select ModelSim from the Tool Name list
select Compile test bench under NativeLink settings.
PCI Compiler Version 10.1
If you are using other simulators, set the location of your
preferred EDA simulation tool executable. This is a global
setting, and needs to be done only once.
®
software
chapter in volume 3 of
Altera Corporation
January 2011
“Step