IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 126

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
3–52
PCI Compiler User Guide
8
9
Table 3–35. Single-Cycle Memory Read Target Transaction (Part 2 of 2)
Clock Cycle
The PCI MegaCore function deasserts
transaction. To satisfy the requirements for sustained tri-state buffers, the PCI MegaCore
function drives
Additionally, the PCI MegaCore function tri-states the
The rising edge of clock cycle 8 signals the end of the last data phase because
deasserted and
also informs the local side that no more data is required by deasserting
lt_tsr[10]
previous clock cycle.
The PCI MegaCore function informs the local-side device that the transaction is complete by
deasserting the
devseln
,
ack64n
1
is asserted to indicate a successful data transfer on the PCI side during the
devseln
lt_tsr[11..0]
irdyn
,
trdyn
The local-side design must ensure that PCI latency rules are not
violated while the PCI MegaCore function waits for data. If the
local-side design is unable to meet the latency requirements, it
must assert lt_discn to request that the PCI MegaCore
function terminate the transaction. The PCI target latency rules
state that the time to complete the first data phase must not be
greater than 16 clock cycles, and the subsequent data phases
must not take more than 8 clock cycles to complete.
PCI Compiler Version 10.1
and
,
ack64n
trdyn
, and
stopn
,
signals. Additionally, the PCI MegaCore function tri-states
are asserted. In clock cycle 8, the PCI MegaCore function
trdyn
trdyn
to begin the turn-around cycle on the PCI bus.
Event
, and
,
devseln
stopn
ad
bus because the cycle is complete.
high during this clock cycle.
, and
ack64n
lt_framen
to end the
Altera Corporation
January 2011
framen
, and
is