IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 19

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 1. PCI-to-DDR2 SDRAM Design Using the PCI Compiler With MegaWizard Flow
Altera Corporation
January 2011
Bus
PCI
Altera FPGA
MegaCore
Function
Altera
PCI
Altera PCI MegaCore Function Local-Side, Low Level Interface
f
Figure 1
the PCI Compiler with MegaWizard Plug-in Manager flow; shaded areas
represent user-customized blocks.
For more information about the PCI Compiler with MegaWizard flow,
refer to
PCI Compiler With SOPC Builder Flow
With this flow, you specify system components and choose system
options from a rich set of features, and the SOPC Builder then
automatically generates the interconnect logic and simulation
environment. Thus, you define and generate a complete system in
dramatically less time than manually integrating separate IP blocks.
1
Backend User Design
Control
Control
Master
Target
Logic
Logic
Chapter 1, Getting
shows a PCI-to-DDR2 SDRAM controller interface design using
This flow is recommended for users who are new to the PCI
Compiler or whose highest priority is to minimize design time.
PCI Compiler Version 10.1
Engine
DMA
FIFOs
Data
Path
Started.
Controller
Interface
SDRAM
DDR2
MegaCore
Controller
Function
SDRAM
About PCI Compiler
DDR2
Altera
7