IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 326

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Control & Status Registers
7–58
PCI Compiler User Guide
7
8
9
10
11
12
13
14:15 Reserved
16
17
18
19
20
21
22
23
31:24 Reserved
Table 7–26. Avalon Interrupt Status Register – Address 0x3060 (Part 2 of 2)
Bit
INTAN_RISE
PCI_PERR_REP
PCI_TABORT_SIG
PCI_TABORT_RCVD
PCI_MABORT_RCVD
PCI_SERR_SIG
PCI_PERR_DET
P2A_MAILBOX_INT0
P2A_MAILBOX_INT1
P2A_MAILBOX_INT2
P2A_MAILBOX_INT3
P2A_MAILBOX_INT4
P2A_MAILBOX_INT5
P2A_MAILBOX_INT6
P2A_MAILBOX_INT7
Name
RW1C
RO
RO
RO
RO
RO
RO
N/A
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
N/A
PCI Compiler Version 10.1
Access
Mode
This bit is set to 1 when the PCI
from 0 to 1. This bit is set to 0 when a '1' is written to it and
intan
This bit is only implemented when the bridge is operating
in the PCI Host-Bridge Device mode.
Reflects the current value of PCI status register bit 8,
reported. This bit can only be cleared through a direct
access to the PCI configuration status register.
Reflects the current value of PCI configuration status
register bit 11, target abort signaled. This bit can only be
cleared through a direct access to the PCI configuration
status register.
Reflects the current value of PCI configuration status
register bit 12, target abort received. This bit can only be
cleared through a direct access to the PCI configuration
status register.
Reflects the current value of the PCI configuration status
register bit 13, master abort received. This bit can only be
cleared through a direct access to the PCI configuration
status register.
Reflects the current value of PCI configuration status
register bit 14, system error signaled. This bit can only be
cleared through a direct access to the PCI configuration
status register
Reflects the current value of PCI configuration status
register bit 15,
Set to 1 when the P2A_MAILBOX0 register is written to.
Set to 1 when the P2A_MAILBOX1 register is written to.
Set to 1 when the P2A_MAILBOX2 register is written to.
Set to 1 when the P2A_MAILBOX3 register is written to.
Set to 1 when the P2A_MAILBOX4 register is written to.
Set to 1 when the P2A_MAILBOX5 register is written to.
Set to 1 when the P2A_MAILBOX6 register is written to.
Set to 1 when the P2A_MAILBOX7 register is written to.
does not transition in the same cycle as the write.
PERR
detected.
Description
intan
Altera Corporation
signal changes
January 2011
PERR