IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 294

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Target Operation
7–26
PCI Compiler User Guide
Response buffer is empty and no more
data is expected from the interconnect
Response buffer is empty, more data is
expected from the interconnect, and less
than eight cycles have elapsed since the
last data phase.
Response buffer is empty, more data is
expected from the interconnect, and
eight cycles have elapsed since the last
data phase
Normal master completion
Prefetchable target burst read crosses
the BAR boundary
Prefetchable target burst read with
cacheline wrap mode
Target abort
Table 7–8. Termination of Prefetchable Target Burst Reads
Termination Condition
Table 7–8
and the resulting actions.
PCI-to-Avalon Address Translation
Figure 7–8
PCI address that are used in the BAR matching process are replaced by an
Avalon-MM base address that is specific to that BAR. The Avalon-MM
base addresses are hardwired from the CB_P2A_AVALON_ADDR_B[0:5]
parameters for each BAR.
lists the reasons for which a burst transfer can be terminated
PCI Compiler Version 10.1
shows the PCI-to-Avalon address translation. The bits in the
The target controller issues a disconnect and the response buffer is
available for re-use.
Wait states are inserted on the PCI bus in an attempt to extend the
burst transaction.
The target controller issues a target disconnect. The data is
discarded when returned from the interconnect, and the response
buffer is available for re-use after all expected data from the
interconnect is discarded.
●
●
●
One data phase worth of data is read and returned and the request is
disconnected. This happens when the burst count exceeds the PCI
BAR boundary
One data phase worth of data is transferred and the request is
disconnected.
Not applicable. The target controller will not terminate a PCI write
operation with a target abort.
Data in the response buffer is discarded.
Data already requested from the interconnect is discarded when
returned.
After all expected data from the interconnect is discarded, the
response buffer is available for re-use.
(Table 7–7 on page
Resulting Action
7–24).
Altera Corporation
January 2011