IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 90

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus Signals
3–16
PCI Compiler User Guide
Note to
(1)
Table 3–5. PCI Status Register Output Bus (stat_reg[6..0]) Bit Definition
Bit Number
This signal is added for compliance with the PCI Local Bus Specification, Revision 3.0.
0
1
2
3
4
5
6
Table
3–5:
tabort_rcvd
mabort_rcvd
int_stat
tabort_sig
perr_rep
serr_sig
perr_det
Bit Name
Table 3–5
Local Address, Data, Command, & Byte Enable Signals
Table 3–6
command, and byte enable signals.
(1)
summarizes the PCI local interface signals for the address, data,
shows definitions for the PCI status register bits.
PCI Compiler Version 10.1
Parity error reported. Status register bit 8.
Target abort signaled. Status register bit 11.
Target abort received. Status register bit 12.
Master abort received. Status register bit 13.
Signaled system error. Status register bit 14.
Parity error detected. Status register bit 15.
Interrupt status. Status register bit 3.
Description
Altera Corporation
January 2011