IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 296

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Master Operation
7–28
PCI Compiler User Guide
The PCI-Avalon bridge uses the burst count to select the best PCI
command that provides the best performance on the PCI bus. For
example, if the burst count is greater than 1, but the request spans more
than one cacheline size (as define by the PCI cacheline size register) the
PCI-Avalon bridge issues a PCI memory read multiple command.
Because the interconnect does not support non-posted write operations,
the PCI-Avalon bridge cannot report the status of I/O or configuration
write operations back to Avalon-MM. So, if you want to emulate a
non-posted write behavior, you can either:
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There are two performance options available in the master mode
operation:
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Avalon-To-PCI Read & Write Operation
The PCI Bus Access Slave port is a burst capable slave that attempts to
create PCI bursts that match the bursts requested from the interconnect.
The PCI-Avalon bridge is capable of handling bursts up to 512 bytes with
a 32-bit PCI bus and 1024 bytes with a 64-bit PCI. In other words, the
maximum supported Avalon-MM burst count is 128.
Bursts from Avalon-MM can be received on any boundary. However,
when internal PCI-Avalon bridge bursts cross the Avalon-to-PCI address
page boundary, they are broken into two pieces. This is because the
address translation can change at that boundary, resulting in a different
PCI address needing to be used for the second portion of the burst with a
burst count greater than 1.
Issue a write immediately followed by a read transaction. When the
read returns, you will know that the write transaction is finished.
Use the current PCI status register bit, A2P_WRITE_IN_PROGRESS,
to determine if the write transaction is still pending in the bridge.
Burst Transfers with Single Pending Read. This performance
profile initiates both PCI single-cycle and burst transactions,
depending on the Avalon-MM burst count. Each PCI delayed read
transaction must complete before a new one is initiated. This
selection maximizes data throughput, but does not minimize PCI
read latencies.
Burst Transfers with Multiple Pending Reads. This performance
profile initiates both PCI single-cycle and burst transactions,
depending on the Avalon-MM burst count. A maximum of four
pending PCI delayed read transactions are allowed. This selection
maximizes data throughput and minimizes PCI read latencies.
PCI Compiler Version 10.1
Altera Corporation
January 2011