IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 68

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Variation File Parameters
2–10
PCI Compiler User Guide
MAX_64_BAR_RW_BITS
NUMBER_OF_BARS
CAP_PTR
CIS_PTR
ENABLE_BITS
Table 2–1. PCI MegaCore Function Parameters (Part 4 of 5)
Name
Decimal
Decimal
Hexadecimal
Hexadecimal
Hexadecimal
Format
PCI Compiler Version 10.1
8
1
H"40"
H"00000000"
H"00000000"
Default Value
Maximum number of read/write bits in upper
BAR when using a 64-bit BAR. This
parameter controls the number of bits
decoded in the high BAR of a 64-bit BAR.
(Values for this parameter are integers from
8 to 32.) For example, setting this parameter
to eight (the default value) allows the user to
reserve up to 512 Gigabytes (GBytes).
Note: Most systems will not require that all
of the upper bits of a 64-bit BAR be
decoded. This parameter controls the size
of the comparator used to decode the high
address of the 64-bit BAR.
Number of base address registers. Only the
logic that is required to implement the
number of BARs specified by this parameter
is used—i.e., BARs that are not used do not
take up additional logic resources. The PCI
MegaCore function sequentially instantiates
the number of BARs specified by this
parameter starting with BAR0. When
implementing a 64-bit BAR, two BARs are
used; therefore, the NUMBER_OF_BARS
parameter should be raised by two.
Capabilities list pointer register. This 8-bit
value sets the capabilities list pointer
register.
CardBus CIS pointer. The CIS_PTR sets
the value stored in the CIS pointer register.
The CIS pointer register indicates where the
CIS header is located. For more
information, refer to the PCMCIA
Specification, version 3.0. The functions
ignore this parameter if CIS_PTR is not set
to 0. In other words, if the CIS_PTR_ENA bit
is set to 1, the functions return the value in
CIS_PTR during a configuration read to the
CIS pointer register. The function returns
H"00000000" during a configuration read
to CIS when CIS_PTR_ENA is set to 0.
Feature enable bits. This parameter is a
32-bit hexadecimal value which controls
whether various features are enabled or
disabled. The bit definition of this parameter
is shown in
Table
Description
2–2.
Altera Corporation
January 2011