IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 171

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
7
8
9
Table 3–38. Zero-Wait State Burst Memory Read Master Transaction (Part 2 of 3)
Clock
Cycle
The function asserts
data phase the function asserts
the local side to indicate that the local side is ready to accept data. For subsequent data phases, the
function does not assert
The target claims the transaction by asserting
address decode. The target also asserts
data.
During this clock cycle, the function also asserts
phase mode.
The target asserts
has already asserted
At the same time,
64-bit data.
The function asserts
PCI side on the previous cycle and is ready to send the data to the local side master interface.
Because
cycle, the function asserts
l_hdat_ackn
Because
rising edge of clock cycle 10.
On the local side, the
asserted during this clock cycle, this action guarantees to the local side that, at most, two more data
phases will occur on the PCI side: one during this clock cycle and another on the following clock cycle
(clock cycle 10). The last data phase on the PCI side takes place during clock cycle 10.
The function also asserts
successful data transfer has occurred on the PCI bus during the previous clock cycle.
lm_rdyn
irdyn
signals indicate to the local side that valid data is available on the
and
lm_tsr[9]
trdyn
was asserted in the previous cycle and
irdyn
lm_ackn
trdyn
irdyn
lm_lastn
irdyn
lm_tsr
to inform the function that it is ready to transfer data. Because the function
lm_dxfrn
to inform the target that the function is ready to receive data. On the first
, a data phase is completed on the rising edge of clock cycle 9.
are asserted, another data phase is completed on the PCI side on the
PCI Compiler Version 10.1
to inform the local side that the function has registered data from the
is asserted to indicate to the local side that the target can transfer
irdyn
unless the local side is ready to accept data.
signal is asserted. Because
[8] in the same clock cycle to inform the local side that a
. The assertion of the
regardless of whether the
ack64n
devseln
Event
lm_tsr[3]
to inform the function that it can transfer 64-bit
. In this case, the target performs a fast
lm_ackn
lm_dxfrn
to inform the local side that it is in data
lm_lastn
lm_rdyn
is asserted in the current
,
l_ldat_ackn
,
irdyn
Functional Description
signal is asserted on
, and
l_dato
trdyn
, and
bus.
3–97
are