IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 235

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Design Flow
Altera Corporation
January 2011
To create a PCI system that uses the PCI Compiler with SOPC Builder,
and to evaluate it using the OpenCore Plus hardware evaluation feature,
include the following steps in your design flow:
1.
2.
3.
4.
5.
6.
7.
Obtain and install the PCI Compiler.
Create a Quartus II project.
Use SOPC Builder and the Quartus II software to generate a system
that uses the PCI-Avalon bridge.
Use MegaWizard to configure the PCI-Avalon bridge.
Use IP functional models to verify your system operation. Although
this step is always recommended, it is more critical if you are using
your own custom-defined SOPC Builder peripheral.
Use an Altera-provided PCI constraint file to ensure your system
meets the timing requirements of the PCI specification.
f
Use the Quartus II software to compile your design and perform
static timing analysis.
1
Purchase a license for the PCI MegaCore function.
PCI Compiler Version 10.1
For more information on obtaining and using
Altera-provided PCI constraint files in your design, refer to
Appendix A, Using PCI Constraint File Tcl
You can generate an OpenCore Plus time-limited
programming file, which you can use to verify the
operation of your design in hardware.
5. Getting Started
Scripts.
5–1