IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 320

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Control & Status Registers
7–52
PCI Compiler User Guide
31:0
Table 7–19. PCI Interrupt Enable Register – Address: 0x0050
Bit
One-to-one enable
mapping to the PCI
interrupt status register
bits
Name
Avalon-MM interrupts can also be enabled for all of the conditions in bits
31:0. However, only one of the Avalon-MM or PCI interrupts (not both)
should be enabled for any given bit. There is typically a single process in
either the PCI or Avalon-MM domain that is responsible for handling the
condition reported by the interrupt.
PCI Mailbox Register Access
The PCI bus typically needs write access to a set of PCI-to-Avalon mailbox
registers and read-only access to a set of Avalon-to-PCI mailbox registers.
Table 7–1 on page 7–5
mailbox registers.
The PCI-to-Avalon mailbox registers are writable at the addresses shown
in
bit in the Avalon-MM interrupt status register to be set to 1.
0x0800
0x0804
0x0808
0x080C
0x0810
0x0814
0x0818
0x081C
Table 7–20. PCI-to-Avalon Mailbox Registers – Address Range:
0x0800-0x081F
Table
RW
Address
Access
Mode
7–20. Writing to one of these registers causes the corresponding
PCI Compiler Version 10.1
P2A_MAILBOX0
P2A_MAILBOX1
P2A_MAILBOX2
P2A_MAILBOX3
P2A_MAILBOX4
P2A_MAILBOX5
P2A_MAILBOX6
P2A_MAILBOX7
When set to 1, indicates that the associated bit in the PCI
interrupt status register will cause the PCI interrupt line
(
register.
Only bits implemented in the PCI interrupt status register are
implemented in the enable register. Unimplemented bits cannot
be set to 1.
intan
lists the specific number (1 or 8) of available
Name
) to be asserted if not disabled by the PCI command
RW
RW
RW
RW
RW
RW
RW
RW
Access
Description
PCI-to-Avalon mailbox 0.
PCI-to-Avalon mailbox 1.
PCI-to-Avalon mailbox 2.
PCI-to-Avalon mailbox 3.
PCI-to-Avalon mailbox 4.
PCI-to-Avalon mailbox 5.
PCI-to-Avalon mailbox 6.
PCI-to-Avalon mailbox 7.
Description
Altera Corporation
January 2011