IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 252

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IP-PCI/MT32

Manufacturer Part Number
IP-PCI/MT32
Description
IP CORE - 32-bit 66MHz PCI Master/Target
Manufacturer
Altera
Type
MegaCorer
Datasheet

Specifications of IP-PCI/MT32

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone, HardCopy II, MAX II, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 32 bit
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
System Options-1
6–2
PCI Compiler User Guide
Selecting the PCI Master/Target Peripheral mode results in the
PCI-Avalon bridge instantiating either the Altera pci_mt32 or
pci_mt64 MegaCore function. Your PCI Data Bus Width selections in
the System Options - 2 tab will make the final determination between
MegaCore functions.
PCI Target-Only Peripheral
This mode allows PCI bus mastering devices to access Avalon-MM slave
devices via the PCI bus target interface. Select this option if you are
constructing an SOPC Builder system that does not have Avalon-MM
master devices accessing PCI bus devices. Refer to
and
Selecting the PCI Target-Only Peripheral mode results in the
PCI-Avalon bridge instantiating either the pci_t32 or pci_t64
MegaCore function. Your PCI Data Bus Width selections in the System
Options - 2 tab will make the final determination between MegaCore
functions.
PCI Host-Bridge Device
In addition to the same features provided by the PCI Master/Target
Peripheral mode, the PCI Host-Bridge Device mode provides host bridge
functionality including hardwiring the master enable bit to 1 in the PCI
command register and allowing self configuration. Hardwiring the
master enable bit to 1 allows the PCI master device to initiate master
transactions upon power up. Self configuration is needed to enable the
PCI-Avalon bridge’s PCI master device to access its own PCI
configuration header for the PCI bus enumeration.
Select PCI Host-Bridge Device mode when the Host processor is on the
Avalon-MM side of the PCI-Avalon bridge. Selecting this mode results in
the PCI-Avalon bridge instantiating either the pci_mt32 or pci_mt64
MegaCore function. Your PCI Data Bus Width selections in the System
Options - 2 tab will make the final determination between MegaCore
functions.
Figure 7–3 on page
PCI Compiler Version 10.1
7–8.
Figure 7–2 on page 7–7
Altera Corporation
January 2011

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