IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 80

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Overview
3–6
PCI Compiler User Guide
Target Device Signals & Signal Assertion
Figure 3–5
the PCI bus in target mode. These signals apply to the pci_mt64,
pci_t64, pci_mt32, and pci_t32 functions when they are operating
in target mode. The signals are grouped by functionality, and signal
directions are illustrated from the perspective of the PCI MegaCore
function operating as a target on the PCI bus. The 64-bit extension signals,
including req64n, ack64n, par64, ad[63..32], and cben[7..4],
are not implemented in the pci_mt32 and pci_t32 functions.
Figure 3–5. Target Device Signals
A 32-bit target sequence begins when the PCI master device asserts
framen and drives the address and the command on the PCI bus. If the
address matches one of the base address registers (BARs) in the PCI
MegaCore function, it asserts devseln to claim the transaction. The
master then asserts irdyn to indicate to the target device for a read
operation that the master device can complete a data transfer, and for a
write operation that valid data is on the ad[31..0] bus.
The PCI MegaCore function drives the control signals devseln, trdyn,
and stopn to indicate one of the following conditions to the PCI master:
■
■
Command
The PCI MegaCore function has decoded a valid address for one of
its BARs and it accepts the transactions (assert devseln)
The PCI MegaCore function is ready for the data transfer (assert
trdyn)
Address,
Interface
System
Control
Signals
Signals
Signals
Data &
PCI Compiler Version 10.1
illustrates the signal directions for a PCI device connecting to
cben[7..0]
ad[63..0]
devseln
ack64n
req64n
framen
par64
stopn
trdyn
irdyn
idsel
rstn
par
clk
Target Device
Altera Corporation
intan
perrn
serrn
January 2011
Error
Reporting
Signals
Interrupt
Request
Signal