IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 150

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–22. 32-Bit Configuration Write Transaction
3–76
PCI Compiler User Guide
lt_tsr[11..0]
cben[3..0]
ad[31..0]
devseln
framen
stopn
trdyn
irdyn
idsel
par
clk
1
2
000
Adr
B
Configuration Write Transactions
Configuration write transactions are 32 bits. Configuration cycles are
automatically handled by the PCI MegaCore functions and do not require
local side actions.
transaction. The configuration write transaction is similar to a 32-bit
single-cycle transaction, except for the following:
■
■
1
3
Adr-PAR
During the address phase, idsel must be asserted in a configuration
transaction
Because the configuration write does not require local side actions,
the PCI MegaCore function asserts trdyn independent from the
lt_rdyn signal
The local side cannot retry, disconnect, or abort configuration
cycles.
4
PCI Compiler Version 10.1
BE0_L
D0_L
5
Figure 3–22
100
D0-L-PAR
6
shows a typical configuration write
7
500
8
9
Altera Corporation
000
January 2011
10
11