IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 72

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Variation File Parameters
2–14
PCI Compiler User Guide
15
16
Number
Table 2–2. Bit Definition of the ENABLE_BITS Parameter (Part 4 of 5)
Bit
DISABLE_LAT_TMR (1)
PCI_64BIT_SYSTEM
Bit Name
PCI Compiler Version 10.1
1
0
Default
Value
Disable master latency timer. This bit controls
whether the latency timer circuitry will operate as
indicated in the PCI Local Bus Specification,
version 3.0. When this bit is set to 0, the latency
timer circuitry will operate normally and will force
the
relinquish bus ownership as soon as possible
when the latency timer has expired and
not asserted. If this bit is set to 1, the latency timer
circuitry is disabled. In this case, the
or
ownership normally when the local side signal
lm_lastn is asserted or when the target
terminates the PCI transaction with a retry,
disconnect, or abort.
64-bit only PCI devices. This bit allows enhanced
master capabilities when the pci_mt64 function
is used in systems where a 64-bit master request
will always be accepted by a 64-bit target device
(target device always responds with
asserted). When this bit is set to 1, the pci_mt64
master will:
Support 64-bit single-cycle master write
transactions
Assert
of
This option should only be used in embedded
applications where the designer controls the
entire system configuration. This option does not
affect target transactions and does not affect
master 32-bit transactions including transactions
using the
transactions.
framen
pci_mt32
pci_mt64
irdyn
lm_req32n
for read and write transactions.
master will relinquish bus
one clock cycle after the assertion
or
pci_mt32
Definition
, configuration, and I/O
Altera Corporation
master to
January 2011
ack64n
pci_mt64
gntn
is