IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 160

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
3–86
PCI Compiler User Guide
Target Abort
Target abort refers to an abnormal termination because either the local
logic detected a fatal error, or the target will never be able to complete the
request. An abnormal termination may cause a fatal error for the
application that originally requested the transaction. A target abort
allows the transaction to complete gracefully, thus preserving normal
operation for other agents.
A target device issues an abort by deasserting devseln and trdyn and
asserting stopn. A target device must set the tabort_sig bit in the PCI
status register whenever it issues a target abort. Refer to
on page 3–33
function issuing an abort during a burst write cycle. It applies to all PCI
MegaCore functions, excluding the 64-bit extension signals as noted for
pci_mt32 and pci_t32.
1
The PCI Local Bus Specification, Revision 3.0 requires that a target
device issues an abort if the target device shares bytes in the
same DWORD with another device, and the byte enable
combination received byte requests outside its address range.
This condition most commonly occurs during I/O transactions.
The local-side device must ensure that this requirement is met,
and if it receives this type of transaction, it must assert
lt_abortn to request a target abort termination.
PCI Compiler Version 10.1
for more details.
Figure 3–30
shows the PCI MegaCore
Altera Corporation
“Status Register”
January 2011