IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 221

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
mem_wr_64
The mem_wr_64 command performs a memory write of the data to the
address provided in the command. This command can perform
single-cycle or burst 64-bit memory write depending on the value of the
qword argument.
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mem_rd_64
The mem_rd_64 command performs memory read transactions with the
address provided in the command argument. This command can perform
single-cycle or burst 64-bit memory read depending on the value of the
qword argument.
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Syntax:
Arguments:
Syntax:
Arguments:
This command performs a single-cycle 64-bit memory write if the
qword value is one.
This command performs a burst-cycle 64-bit memory write if the
qword value is greater than one. In a burst transaction, the first data
phase uses the data value provided in the command. The
subsequent data phases use values incremented sequentially by one
from the data provided in the command argument.
If the qword value is one the command performs a single-cycle
transaction.
If the qword value is greater than one the command performs a burst
transaction.
PCI Compiler Version 10.1
mem_rd_32(address, qword)
address
qword
mem_wr_64(address, data, qword)
address
data
qword
Transaction address. This value must be in
hexadecimal radix.
The number
one indicates a single-cycle memory read
transaction. A value greater than one indicates a
burst transaction. This value must be an integer.
Transaction address. This value must be in
hexadecimal radix.
Data used for first data phase. Subsequent
data phases use a value sequentially
incremented by one from this data. This value
must be in hexadecimal radix.
The number
A value of one indicates a single-cycle
memory write transaction. A value greater
than one indicates a burst transaction. This
value must be an integer.
QWORD
QWORD
s read in the transaction. A
PCI Compiler User Guide
s written in a transaction.
Testbench
4–11