IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 133

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Figure 3–12
read target transaction. (This figure only applies to the pci_mt64 and
pci_t64 functions.)
The events in
except that a 64-bit transfer shown in
the local side but requires two clock cycles on the PCI side. The function
automatically inserts local side wait states in clock cycles 7 and 9 to
temporarily suspend the local transfer allowing sufficient time for the
data to be transferred on the PCI side. In
asserted and lt_tsr[9] is asserted indicating that the transaction is a
32-bit burst. If the local side cannot handle 32-bit burst transactions, it
must disconnect after the first local transfer.
Also, because the address of the transaction is not at a QWORD boundary
(ad[2..0] == B"100"), the first DWORD transferred to the PCI side is
the high DWORD. The first low DWORD is not transferred to the PCI side.
The pci_mt64 and pci_t64 functions deassert l_ldat_ackn and
assert l_hdat_ackn during the first data transfer on the local side to
indicate that only the high DWORD is transferred to the PCI side, as shown
in
Figure 3–12
PCI Compiler Version 10.1
shows a 32-bit PCI side and 64-bit local side burst memory
Figure 3–12
at clock cycle 7.
are the same as those shown in
Figure 3–12
Figure
3–12, lt_tsr[7] is not
takes one clock cycle on
Functional Description
Figure
3–8,
3–59