IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 83

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
Completer Only PCI Express Endpoint Single DWord
Completer Only PCI Express Endpoint Single DWord
Figure 4–14. Design Including PCI Express Endpoint Completer Only Single DWord SOPC Builder Component
December 2010 Altera Corporation
SOPC Builder System
Avalon-MM
Avalon-MM
Slave
Slave
PCI Express RX Block
.
.
.
Interconnect
Avalon-MM
The completer only single dword endpoint is intended for applications that use PCI
Express to perform simple read and write register accesses from a host CPU. The
completer only single dword endpoint is available for SOPC Builder systems and
includes an Avalon-MM interface to the application layer. This endpoint is not
pipelined; at any time a single request can be outstanding.
The completer-only single dword endpoint supports the following requests:
■
■
■
Figure 4–14
completer-only single dword IP core.
As this figure illustrates, the PCI Express IP core links to a PCI Express root complex.
A bridge component includes PCIe TX and RX blocks, a PCIe RX master, and an
interrupt handler. It connects to the FPGA fabric using an Avalon-MM interface. The
following sections provide an overview of each of block in the bridge.
The PCI Express RX control logic interfaces to the hard IP PCI Express core to process
requests from the root complex. It supports memory reads and writes of a single
dword. It generates a completion with Completer Abort (CA) status for reads greater
than four bytes and discards all write data without further action for write requests
greater than four bytes.
System
Fabric
Read and write requests of a single dword (32 bits) from the root complex
Completion with completer abort status generation for other types of non-posted
requests
INTX or MSI support with one interrupt source
PCI Express Endpoint, Completer Only Single DWord
SOPC Builder Component
shows a SOPC Builder system that includes a the PCI Express
Bridge
Avalon-MM
Master Rx
Interrupt
Handler
PCIe Rx
PCIe Tx
Hard IP Core
PCI Express
PCI Express Compiler User Guide
PCIe Link
to Host
CPU
Root Complex
PCI Express
4–25