IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 260

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–32
PCI Express Compiler User Guide
If addr_map_4GB_limit is 0, the resulting memory space map is shown in
Figure
Figure 15–8. Memory Space Layout—No Limit
15–8.
0xFFFF FFFF FFFF FFFF
0x0000 0001 0000 0000
BAR size dependent
BAR size dependent
BAR size dependent
0x001F FFC0
0x001F FF80
0x0000 0000
0x0020 0000
Addr
not writable by user calls
not writable by user calls
Endpoint Memory Space
Endpoint Memory Space
Used by BFM routines
Used by BFM routines
Root Complex Shared
Configuration Scratch
Prefetchable Memory
Assigned Smallest to
Assigned Smallest to
Assigned Smallest to
(Prefetchable 32
(Prefetchable 64
Endpoint Non
Space BARs
or endpoint
or endpoint
BAR Table
Memory
Unused
Unused
Largest
Largest
Largest
Space
BARs
BARs
Chapter 15: Testbench and Design Example
-
bit)
bit)
December 2010 Altera Corporation
Root Port BFM