MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 118

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Timer Interface Module (TIM)
MSxA — Mode Select Bit A
ELSxB and ELSxA — Edge/Level Select Bits
118
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See
Table
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin.
the ELSxB and ELSxA bits.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Table
8-3. Reset clears the MSxA bit.
8-3.
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
MSxB:MSxA
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
X0
X1
1X
1X
1X
00
00
00
01
01
01
Table 8-3. Mode, Edge, and Level Selection
ELSxB:ELSxA
00
00
01
10
11
01
10
11
01
10
11
Table 8-3
Output compare
Buffered output
buffered PWM
Output preset
Input capture
compare or
NOTE
or PWM
Mode
shows how ELSxB and ELSxA work. Reset clears
Capture on falling edge only
Capture on rising edge only
Toggle output on compare
Toggle output on compare
Clear output on compare
Clear output on compare
Set output on compare
Set output on compare
Pin under port control;
initial output level high
Pin under port control;
initial output level low
Capture on rising or
Configuration
falling edge
Freescale Semiconductor