MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 31

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
# Non-volatile FLASH registers; write by programming.
Addr.
$FE0C
$FE0D
$FFCF
$FE0B
$FE0E
$FFD0
$FFFF
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
↓
U = Unaffected
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
Break Status and Control
FLASH Control Register
Register Name
COP Control Register
Mask Option Register
FLASH Block Protect
Break Address High
Break Address low
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(BRKSCR)
(COPCTL)
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
(FLBPR)
Reserved
Reserved
Register
Register
Register
Register
(BRKH)
(MOR)
(FLCR)
(BRKL)
(INT1)
(INT2)
(INT3)
#
#
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
OSCSEL
BRKE
BPR7
Bit15
Bit 7
X = Indeterminate
IF14
Bit7
IF6
R
R
R
R
R
0
0
0
0
0
0
0
0
0
BRKA
BPR6
Bit14
IF13
Bit6
IF5
R
R
R
R
R
R
6
0
0
0
0
0
0
0
0
0
BPR5
Bit13
IF12
Bit5
IF4
R
R
R
R
R
R
5
0
0
0
0
0
0
0
0
0
0
Writing clears COP counter (any value)
Unaffected by reset; $FF when blank
Unaffected by reset; $FF when blank
Low byte of reset vector
= Unimplemented
Unaffected by reset
BPR4
Bit12
IF11
Bit4
IF3
R
R
R
R
R
R
4
0
0
0
0
0
0
0
0
0
0
HVEN
BPR3
Bit11
Bit3
R
R
R
R
R
R
3
0
0
0
0
0
0
0
0
0
0
0
MASS
BPR2
Bit10
Bit2
IF1
R
R
R
R
R
R
R
2
0
0
0
0
0
0
0
0
0
0
= Reserved
ERASE
BPR1
Bit9
Bit1
IF8
R
R
R
R
R
R
1
0
0
0
0
0
0
0
0
0
0
Monitor ROM
BPR0
PGM
Bit 0
IF15
Bit8
Bit0
IF7
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
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