MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 42

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Configuration and Mask Option Registers (CONFIG & MOR)
3.3 Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
LVID — Low Voltage Inhibit Disable Bit
SSREC — Short Stop Recovery Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
42
COPRS selects the COP time-out period. Reset clears COPRS.
(See
LVID disables the LVI module. Reset clears LVID.
(See
SSREC enables the CPU to exit stop mode with a delay of
32 ICLK cycles instead of a 4096 ICLK cycle delay.
STOP enables the STOP instruction.
COPD disables the COP module. Reset clears COPD.
(See
1 = COP timeout period is (2
0 = COP timeout period is (2
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
Chapter 14 Computer Operating Properly
Chapter 15 Low Voltage Inhibit
Chapter 14 Computer Operating Properly
Address:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
Reset:
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
COPRS
$001F
Bit 7
R
0
Figure 3-1. Configuration Register 1 (CONFIG1)
= Reserved
R
6
0
13
18
– 2
– 2
(LVI).)
4
4
) ICLK cycles
) ICLK cycles
R
5
0
NOTE
LVID
(COP).)
(COP).)
4
0
R
3
0
SSREC
2
0
STOP
1
0
Freescale Semiconductor
COPD
Bit 0
0