MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 159

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

DDRD[7:0] — Data Direction Register D Bits
When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Address:
DDRD Bit
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
port D I/O logic.
Reset:
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
0
1
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRD7
$0007
Bit 7
0
PTD Bit
Figure 11-11. Data Direction Register D (DDRD)
X
X
(1)
DDRD6
6
0
Table 11-4. Port D Pin Functions
I/O Pin Mode
RESET
Input, Hi-Z
Figure 11-12. Port D I/O Circuit
Output
DDRD5
5
0
(2)
Table 11-4
NOTE
Accesses to DDRD
DDRD4
DDRDx
PTDx
4
0
Read/Write
DDRD[7:0]
DDRD[7:0]
summarizes the operation of the port D pins.
DDRD3
3
0
Figure 11-12
DDRD2
2
0
PTD[7:0]
PTDPU[6:7]
Read
Pin
Accesses to PTD
To ADC, TIM1, SCI
DDRD1
1
0
shows the
PTD[7:0]
PTD[7:0]
Write
DDRD0
Bit 0
PTDx
0
(3)
Port D
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